With the progress of technologies, the people have a higher and higher requirement on the performance of a processor. Corresponding to the requirement, the people have developed processor systems with stronger processing capabilities, for example, processor system architectures such as SMP (Symmetric Multi-Processor, symmetric multi-processor) system, Cluster (cluster) system, MPP (Massive Parallel Processing, massive parallel processing) system, and NUMA (Non Uniform Memory Access, non uniform memory access) system. The architectures achieve system performance improvement mainly in a manner of sharing a memory and an IO bus. For example, in the architecture of the NUMA system, nodes are connected and exchange information with each other through an interconnection module, and under one OS (operating system), share all CPUs and share memories of the whole system, and thereby performance optimization and improvement of the processor system is achieved.
At present, both the SMP system and the NUMA system adopt a redundant link solution with dual NC (Node Controller, node controller) chips. When a failure occurs in one of the NC links, all services on the NC link are switched to the other redundant NC link to ensure that the services are not interrupted and the performance of the processor system is not affected, and thereby the availability of the whole processor system is improved.
The prior art at least has the following disadvantages.
Because of the high cost and long development cycle of the NC chip, the cost of the deployment of the redundant NC link is excessively high. Furthermore, the redundant NC link has a very low utilization ratio but still occupies bus (such as a QPI (QuickPath Interconnect) interface and an HT (HyperTransport) bus) resources of the processor system, which goes against the expansion of the processor system when the bus resources of the processor system are insufficient